1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to an input buffer circuit for a data bus.
2. Description of the Related Art
Conventional semiconductor integrated circuits such as microprocessors are normally so constructed that a control signal indicative of an input timing is generated from a bus control circuit to control an input buffer for an external bus in order to fetch information on the external bus with a particular timing. An example of the conventional apparatus is described below.
FIG. 1 is a block diagram showing a model of a microprocessor and a memory interface. Microprocessor 15 and memory system 16 are interconnected by address bus 18, control signal paths 110 and 120, and data bus 24. Address bus 18 sends an address signal from microprocessor 15 to memory 16. Control signal path 110 serves as a signal path for R/W (Read and Write) signal 19, BCYST (Bus Cycle Start) signal 20 and DA (Data Access) signal 21 from microprocessor 110. R/W signal 19 is an instruction signal from microprocessor 15 which indicates writing by its low level and reading by its high level. BCYST signal 20 is a negative logic instruction signal from microprocessor 15 which indicates start of a bus cycle. DA signal 21 is a negative logic signal from microprocessor 15 which indicates a timing for access to data. Bidirectional data bus 24 is a signal path which transfers data between microprocessor 15 and memory system 16. Control signal path 120 serves as signal path for READY signal 22 and SZRQ (Size Request) signal 23 from memory system 16. READY signal 22 is a negative logic signal for indicating that memory system 16 is ready to transfer data. SZRQ signal 23 is a negative logic signal for indicating that data must be transferred with the 16-bit unit. Further, clock signal 17 is an internal clock signal of microprocessor 15.
When microprocessor 15 has a 32-bit unit bus, in order to minimize system cost and assure an interface with a 16-bit peripheral apparatus, the function of limiting the bus available to transfer 16-bit data, that is, the bus sizing function, is prepared in the normal manner. Here, data transfer without bus sizing is described first.
FIG. 2 shows a timing chart of a memory read bus cycle without bus sizing. The relationship between data and control signals between microprocessor 15 and memory system 16 is described below with reference to FIGS. 1 and 2. When microprocessor 15 starts to read data from memory system 16, microprocessor 15 inputs a memory address for reading into address bus 18 (transition 601) in synchronism with a rising edge of clock signal 17, simultaneously, R/W signal 19 changes to a high level to designate read-out (transition 602), and thereafter makes BCYST signal 20 active (transition 603). Memory system 16 prepares, information stored at the designated address according to the data inputted by microprocessor 15 and maintains READY signal 22 inactive (transition 605, "transition" is omitted hereafter) until it is prepared to output the information to data bus 24.
Microprocessor 15 inputs BCYST signal 20 active only for one clock interval at the same time as it inputs the memory address, and renders DA signal 21 active in place of rendering BCYST signal 20 inactive, thence thereby causing READY signal 22 to wait for memory system 16 (604). Memory system 16 send the designated data for the read-out into data bus 24 (607) and renders READY signal 22 active (606). While microprocessor 15 keeps DA signal 21 active, it samples READY signal 22 for each clock at the timing of the rising edge of the clock, and if it detects an active state, it fetches the data on data bus 24 into an internal buffer memory thereof at the timing of the rising edge of the next clock (608).
Through the operations described above, microprocessor 15 can read out data at any address from memory system 16.
Next, the case when bus sizing is involved is described with reference to FIG. 1 and to FIG. 3 which shows a timing chart upon bus sizing. In the example shown here, 32-bit data can be transferred by two operations for each 16 bits using SZRQ signal 23. As the bus cycle of microprocessor 15 is extended using READY signal 22 until memory system 16 is prepared to output data as shown in FIG. 2, memory system 16 is able to request the issue of an additional BCYST signal for transferring the upper 16 bits by causing microprocessor 15 recognizes that the bus cycle is sized using SZRQ signal 23. When microprocessor 15 starts to read out 32-bit data from memory system 16, a memory address for read-out is first sent into address bus 18 in synchronism with the rising edge of clock signal 17 (701), simultaneously R/W signal 19 is sent with a high level (702), and thereafter renders BCYST signal 20 active (low level) (703). Due to the request by the inputted signal, memory system 16 prepares information stored at the designated address and renders and thereafter maintains READY signal 22 inactive (high level) until it is prepared to output the information through data bus 24 (705). Microprocessor 15 renders BCYST signal 20 active during only one clock interval and then renders DA signal 21 active (low level) in place of BCYST signal 20 and thereafter waits for READY signal 22 outputted from memory system 16 (704).
Memory system 16 outputs only the lower 16 bits of the 32-bit data designated for read-out into data bus 24 for the lower 16 bits (709) and simultaneously renders READY signal 22 and SZRQ signal 23 active (706, 707). While microprocessor 15 keeps DA signal 21 active, it samples READY signal 22 and SZRQ signal 23 for every falling edge of the clock signals, and if it detects an active level of READY signal 22, it fetches data on data bus 24 into the internal buffer memory thereof at the timing of the rising edge of the next clock (710). In this instance, since SZRQ signal 23 detected at the same time is active, microprocessor 15 recognizes that only the lower 16 bits of the read in from data bus 24 are valid and an additional bus cycle for the upper 16 bits must necessarily be issued. Then, microprocessor 15 issues a bus cycle again by R/W signal 19, BCYST signal 20 and DA signal 21 via address bus 18. Since reading of the upper 16 bits by issuing the additional bus cycle is similar to the operation of the preceding reading bus cycle for the lower 16 bits, description thereof is omitted herein.
FIG. 4 is a circuit diagram of a conventional input buffer circuit. The conventional input buffer circuit includes NOR gate 12 to which lower data input terminal 4 is connected and READY terminal 3 is connected via latch 7 and another latch 8. The output terminal of NOR gate 12 is connected to a data input terminal of data latch 14. Upper data input terminal 1 and the output terminal of latch 8 are connected to the two input terminals of another NOR gate 11, and the output terminal of NOR gate 11 is connected to the input terminal of another data latch 13. The output terminals of data latches 13 and 14 serve as the output terminals of the input buffer circuit. It should be noted that the configuration described above is actually provided by 16 sets in the input buffer circuit, but only one set is shown in FIG. 4 for simplification of illustration.
Functions of the components described above are described hereunder. Upper data input terminal 1 inputs the upper 16 bits of data bus 24. The lower 16 bits of data bus 24 are inputted to lower data input terminal 4. READY terminal 3 is an input terminal through which a negative logic signal which communicates that preparations for transfer of data have been made at memory system 16 is inputted. Each of latches 7 and 8 synchronize a signal inputted thereto asynchronously from READY terminal 3 at the timing of the rising edge of the clock signal to make IREADY signal 80 for the input buffer circuit. Each of NOR gates 11 and 12 masks the inputted data through upper data input terminal 1 and lower data input terminal 4, respectively, to output a low level for any period other than when IREADY signal 80 exhibits a low level. Data latch 13 latches the output of NOR gate 11 at the timing of the rising edge of the clock signal. Data latch 14 latches the output of NOR gate 12 at the timing of the rising edge of the clock signal. It is assumed that clock signal CLK and reverse clock signal CLKB do not overlap each other at either a high level outputs or low level outputs due to a phase delay.
Operation of the conventional apparatus is described below with reference to the timing charts shown in FIGS. 2 and 3 and the circuit diagram shown in FIG. 4.
READY signal 22, which has been rendered active at timing 606 by memory system 16, is applied to READY terminal 3 and is synchronized with the falling edge of the clock signal by latches 7 and 8, and thereafter controls NOR gates 11 and 12 so that data inputted from upper data input terminal 1 and lower data input terminal 4 are applied to data latches 13 and 14, respectively. Data latches 13 and 14 individually latch the data inputted thereto synchronously with the next rising edge of the clock signal.
Operation of the apparatus shown in FIG. 4, wherein bus sizing is involved, is similar to the case described above, and lower data inputted in a first bus cycle and upper data inputted in a second bus cycle are combined by internal processing of microprocessor 15 and are used as 32-bit data. However, since no information of the bus sizing has been transmitted to the input buffer circuit itself, although data are applied only to lower data input terminal 4, both of data latch 13 for the upper 16 bits and data latch 14 for the lower 16 bits will detect an active state of READY signal 22 and latch all the value on the data bus at the timing of the rising edge of the next clock CLKB. In this instance, while there is the possibility that upper data input terminal 1 connected to the data bus presents an intermediate potential since it is not driven, data latch 13 for the upper 16 bits may latch the potential conditions of upper data input terminals 1 as is. This results in the drawback that power dissipation is increased because, even where the input buffer circuit is constructed with a CMOS (Complementary Metal Oxide Semiconductor) in order to minimize power dissipation, when the potential at the data bus is an intermediate potential, both P-channel type insulated gate field effect transistors and N-channel type insulated gate field effect transistors which constitute the upper data side circuit of the input buffer circuit simultaneously enter into a conductive condition causing through-current to flow from power source lines to grounding lines.
With the conventional input buffer circuit described above, when bus sizing is involved, there is the possibility that the upper data side of the data bus may be at an intermediate potential since it is not driven from the outside, and data latch 13, which is a circuit on the upper data side of the input buffer circuit, may fetch the intermediate potential. In this instance, transistors constituting data latch 13 become stabilized linearly, accordingly, the conventional input buffer circuit has the drawback that, even where the circuit is constructed with a CMOS, power dissipation is increased since the through-current flows from power source lines to grounding lines via the transistors.